by Faculty
Filters: author is Ivanov1989
"An analysis of the probabilistic behavior of linear feedback signature registers",
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (USA), vol. 8, pp. 1074-88, oct.
Abstract
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1990
"Computing the error escape probability in count-based compaction schemes",
1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.90CH2924-9), Santa Clara, CA, USA, IEEE Comput. Soc. Press, pp. 368-71, 1990 .
Abstract
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1991
"Iterative algorithms for computing aliasing probabilities",
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (USA), vol. 10, pp. 260-5, feb.
Abstract
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1992
"A multiple signature compaction scheme for BIST",
Microelectron. J. (UK), vol. 23, pp. 205-14, may.
Abstract
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"Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms",
Integr. VLSI J. (Netherlands), vol. 13, pp. 17-38, may.
Abstract
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"Count-based BIST compaction schemes and aliasing probability computation",
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (USA), vol. 11, pp. 768-77, jun.
Abstract
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"A fuzzy multiple signature compaction scheme for BIST",
Proceedings. First Asian Test Symposium (ATS '92) (Cat. No.TH0458-0), Hiroshima, Japan, IEEE Comput. Soc. Press, pp. 247-52, 1992 .
Abstract
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"A minimal hardware overhead BIST data compaction scheme",
Proceedings of Fifth Annual IEEE International ASIC Conference and Exhibit (Cat. No.92TH0475-4), Rochester, NY, USA, IEEE, pp. 368-71, 1992 .
Abstract
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"Accelerated path delay fault simulation",
Digest of Papers. 1992 IEEE VLSI Test Symposium. 10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip (Cat. No.92TH0437-4), Atlantic City, NJ, USA, IEEE, pp. 1-6, 1992 .
Abstract
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"Design framework for a mobile data link protocol",
1992 IEEE International Conference on Selected Topics in Wireless Communications. Conference Proceedings (Cat. No.92TH0462-2), Vancouver, BC, Canada, IEEE, pp. 44-7, 1992 .
Abstract
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1993
"A variable rate constraint length K=5 Viterbi decoder for 12 Mb/s",
1993 Canadian Conference on Electrical and Computer Engineering (Cat. No.93TH0590-0), vol. vol.1, Vancouver, BC, Canada, IEEE, pp. 582-5, 1993 .
Abstract
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"An integrated functional tester for CMOS logic",
1993 Canadian Conference on Electrical and Computer Engineering (Cat. No.93TH0590-0), vol. vol.1, Vancouver, BC, Canada, IEEE, pp. 453-6, 1993 .
Abstract
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"Minimal hardware multiple signature analysis for BIST",
Digest of Papers. Eleventh Annual 1993 IEEE VLSI Test Symposium (Cat. No.93TH0537-1), Atlantic City, NJ, USA, IEEE Comput. Soc. Press, pp. 17-20, 1993 .
Abstract
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"On fault coverage in VLSI built-in self-test with multiple intermediate signature analysis",
1993 Canadian Conference on Electrical and Computer Engineering (Cat. No.93TH0590-0), vol. vol.1, Vancouver, BC, Canada, IEEE, pp. 449-52, 1993 .
Abstract
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1994
"On the testability of CMOS feedback amplifiers",
1994 Proceedings. The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (Cat. No.94TH78009), Montreal, Que., Canada, IEEE Comput. Soc. Press, pp. 65-73, 1994 .
Abstract
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1995
"Fault simulation and testing of an OTA biquadratic filter",
1995 IEEE Symposium on Circuits and Systems (Cat. No.95CH35771), vol. vol.3, Seattle, WA, USA, IEEE, pp. 1764-7, 1995 .
Abstract
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1996
"Programmable BIST space compactors",
IEEE Trans. Comput. (USA), vol. 45, pp. 1393-404, dec.
Abstract
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"Design for testability and built-in self-test of integrated circuits and systems: how these can add value to your products",
38th Midwest Symposium on Circuits and Systems. Proceedings (Cat. No.95CH35853), vol. vol.2, Rio de Janeiro, Brazil, IEEE, pp. 712-17, 1996 .
Abstract
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1997
"Power supply current monitoring techniques for testing PLLs",
Proceedings. Sixth Asian Test Symposium (ATS'97) (Cat. No.97TB100205), Akita, Japan, IEEE Comput. Soc, pp. 366-71, 1997 .
Abstract
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1998
"Non-intrusive testing of high-speed CML circuits",
Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259), Singapore, IEEE Comput. Soc, pp. 172-8, 1998 .
Abstract
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"Testing for floating gates defects in CMOS circuits",
Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259), Singapore, IEEE Comput. Soc, pp. 228-36, 1998 .
Abstract
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1999
"A built-in current monitor for testing analog circuit blocks",
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), vol. vol.2, Orlando, FL, USA, IEEE, pp. 109-14, 1999 .
Abstract
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"A built-in current sensor for testing analog circuit blocks",
IMTC/99. Proceedings of the 16th IEEE Instrumentation and Measurement Technology Conference (Cat. No.99CH36309), vol. vol.3, Venice, Italy, IEEE, pp. 1403-8, 1999 .
Abstract
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"A current integrator for BIST of mixed-signal ICs",
Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), Dana Point, CA, USA, IEEE Comput. Soc, pp. 311-18, 1999 .
Abstract
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2000
"Catastrophic short and open fault detection in bipolar CML circuits: a case study",
J. Electron. Test., Theory Appl. (Netherlands), vol. 16, pp. 631-4, dec.
Abstract
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2001
"A packet switching communication-based test access mechanism for system chips",
Proceedings IEEE European Test Workshop. ETW 2001, Stockholm, Sweden, IEEE Comput. Soc, pp. 81-6, 2001 .
Abstract
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"Design of an optimal test access architecture using a genetic algorithm",
Proceedings 10th Asian Test Symposium, Kyoto, Japan, IEEE, pp. 205-10, 2001 .
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"On the detectability of CMOS floating gate transistor faults",
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (USA), vol. 20, pp. 116-28, 2001 .
Abstract
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2002
"Embedded servo loop for ADC linearity testing",
Microelectron. J. (UK), vol. 33, pp. 773-80, oct.
Abstract
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"CMOS differential and absolute thermal sensors",
J. Electron. Test., Theory Appl. (Netherlands), vol. 18, pp. 295-304, jun.
Abstract
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"Dedicated autonomous scan-based testing (DAST) for embedded cores",
Proceedings International Test Conference 2002 (Cat. No.02CH37382), Baltimore, MD, USA, IEEE, pp. 1176-83, 2002 .
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2003
"An embedded autonomous scan-based results analyzer (EARA) for SoC cores",
Proceedings 21st IEEE VLSI Test Symposium, Napa, CA, USA, IEEE Comput. Soc, pp. 293-8, 2003 .
Abstract
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"Analog IP design flow for SoC applications",
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (Cat. No.03CH37430), vol. vol.4, Bangkok, Thailand, IEEE, pp. 676-9, 2003 .
Abstract
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"Design of a switch for network on chip applications",
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (Cat. No.03CH37430), vol. vol.5, Bangkok, Thailand, IEEE, pp. 217-20, 2003 .
Abstract
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"High-throughput switch-based interconnect for future SoCs",
Proceedings 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, Calgary, Alta., Canada, IEEE Comput. Soc, pp. 304-10, 2003 .
Abstract
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"Reducing test time of embedded SRAMs",
Records of the 2003 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, USA, IEEE, pp. 47-52, 2003 .
Abstract
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"Switch-based interconnect architecture for future systems on chip",
Proc. SPIE - Int. Soc. Opt. Eng. (USA), vol. 5117, Maspalomas, Gran Canaria, Spain, SPIE-Int. Soc. Opt. Eng, pp. 228-37, 2003 .
Abstract
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"Time domain multiplexed TAM: implementation and comparison",
Proceedings Design, Automation and Test in Europe Conference and Exhibition, Munich, Germany, IEEE Comput. Soc, pp. 732-7, 2003 .
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"Yield, overall test environment timing accuracy, and defect level trade-offs for high-speed interconnect device testing",
Proceedings of the Twelfth Asian Symposium, ATS 2003, Xi'an, China, IEEE Comput. Soc, pp. 348-53, 2003 .
Abstract
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2004
"Indirect test architecture for SoC testing",
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (USA), vol. 23, pp. 1128-42, jul.
Abstract
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"Jitter models for the design and test of Gbps-speed serial interconnects",
IEEE Des. Test Comput. (USA), vol. 21, pp. 302-13, jul.
Abstract
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"A scalable communication-centric SoC interconnect architecture",
Proceedings. 5th International Symposium on Quality Electronic Design, San Jose, CA, USA, IEEE Comput. Soc, pp. 343-8, 2004 .
Abstract
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"Designs for reducing test time of distributed small embedded SRAMs",
Proceedings. 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cannes, France, IEEE Comput. Soc, pp. 120-8, 2004 .
Abstract
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"Evaluation of MP-SoC interconnect architectures: a case study",
4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada, IEEE Comput. Soc, pp. 253-6, 2004 .
Abstract
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"Jitter models and measurement methods for high-speed serial interconnects",
Proceedings. International Test Conference 2004 (IEEE Cat. No.04CH37586), Charlotte, NC, USA, IEEE, pp. 1295-302, 2004 .
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"Open defects detection within 6T SRAM cells using a No Write Recovery Test Mode",
Proceedings. 17th International Conference on VLSI Design, Mumbai, India, IEEE Comput. Soc, pp. 493-8, 2004 .
Abstract
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"Reducing embedded SRAM test time under redundancy constraints",
Proceedings. 22nd IEEE VLSI Test Symposium, Napa Valley, CA, USA, IEEE Comput. Soc, pp. 237-42, 2004 .
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2005
"Timing analysis of network on chip architectures for MP-SoC platforms",
Microelectron. J. (UK), vol. 36, pp. 833-45, sep.
Abstract
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"Crosstalk bounded uncorrelated jitter (BUJ) for high-speed interconnects",
IEEE Trans. Instrum. Meas. (USA), vol. 54, pp. 1800-10, oct.
Abstract
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"A realistic timing test model and its applications in high-speed interconnect devices",
J. Electron. Test., Theory Appl. (Netherlands), vol. 21, pp. 621-30, dec.
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"A 0.18 ?m CMOS pipelined encoder for a 5 GS/s 4-bit flash analogue-to-digital converter",
Can. J. Electr. Comput. Eng. (Canada), vol. 30, pp. 183-7, 2005 .
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"A 0.35 ?m CMOS comparator circuit for high-speed ADC applications",
IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat. No. 05CH37618), vol. Vol. 6, Kobe, Japan, IEEE, pp. 6134-7, 2005 .
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"A 4-bit 5 GS/s flash A/D converter in 0.18 ?m CMOS",
IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat. No. 05CH37618), vol. Vol. 6, Kobe, Japan, IEEE, pp. 6138-41, 2005 .
Abstract
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"A fast diagnosis scheme for distributed small embedded SRAMs",
Proceedings. Design, Automation and Test in Europe, vol. Vol. 2, Munich, Germany, IEEE Comput. Soc, pp. 852-7, 2005 .
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"A retention-aware test power model for embedded SRAM",
Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference 2005 (IEEE Cat. No.05EX950C), vol. Vol. 2, Shanghai, China, IEEE, pp. 1180-3, 2005 .
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"Effect of traffic localization on energy dissipation in NoC-based interconnect",
IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat. No. 05CH37618), vol. Vol. 2, Kobe, Japan, IEEE, pp. 1774-7, 2005 .
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"Methodologies and algorithms for testing switch-based NoC interconnects",
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, USA, IEEE Comput. Soc, pp. 238-46, 2005 .
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"Performance evaluation and design trade-offs for network-on-chip interconnect architectures",
IEEE Trans. Comput. (USA), vol. 54, pp. 1025-40, 2005 .
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"SRAM retention testing: zero incremental time integration with March algorithms",
Proceedings. 23rd IEEE VLSI Test Symposium, Palm Springs, CA, USA, IEEE Comput. Soc, pp. 66-71, 2005 .
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2006
"System-on-chip: reuse and integration",
Proc. IEEE (USA), vol. 94, pp. 1050-69, jun.
Abstract
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"Crosstalk in QCA Arithmetic Circuits",
Proc. of SPIE, vol. 6313, San Diego, CA, USA, pp. 631306.1-631306.9, 2006.
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"A DDJ calibration methodology for high-speed test and measurement equipments",
2005 IEEE International Test Conference (IEEE Cat. No.05CH37661C), Austin, TX, USA, IEEE, pp. 10 pp., 2006 .
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"An encoder for a 5GS/s 4-bit flash ADC in 0.18?m CMOS",
2005 Canadian Conference on Electrical and Computer Engineering, Saskatoon, Sask., Canada, IEEE, pp. 698-701, 2006 .
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"BIST for network-on-chip interconnect infrastructures",
Proceedings. 24th IEEE VLSI Test Symposium, Berkeley, CA, USA, IEEE Computer Society, pp. 6 pp., 2006 .
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"Fast detection of data retention faults and other SRAM cell open defects",
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (USA), vol. 25, pp. 167-80, 2006 .
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"NoC interconnect yield improvement using crosspoint redundancy",
2006 21st IEEE International Symposium On Defect and Fault Tolerance in VLSI Systems, Arlington, VA, USA, IEEE Computer Society, pp. 9 pp., 2006 .
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"On-line fault detection and location for NoC interconnects",
12th IEEE International On-Line Testing Symposium, Lake Como, Italy, IEEE Comput. Soc, pp. 6 pp., 2006 .
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"Ultra-low power 90nm 6T SRAM cell for wireless sensor network applications",
2006 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 06CH37717C), Island of Kos, Greece, IEEE, pp. 4 pp., 2006 .
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2007
"Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip",
Integr. VLSI J. (Netherlands), vol. 40, pp. 149-60, feb.
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"Two-point maximum entropy noise discrimination in spectra over a range of baseline offsets and signal-to-noise ratios",
Appl. Spectrosc. (USA), vol. 61, pp. 157-64, feb.
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"On the Error Effects of Random Clock Shifts in Quantum Cellular Automata Circuits",
In Proceedings of 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2007, Rome, Italy, pp. 487-495, 2007.
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"Towards open network-on-chip benchmarks",
2007 International Symposium on Networks-on-Chip, Princeton, NJ, USA, IEEE Computer Society, pp. 8 pp., 2007 .
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2008
"Quantum Mechanical Simulation of QCA with a Reduced Hamiltonian",
IEEE Nano 2008, Arlington, Texas, pp. 327-330, 18/08/2008.
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"Testing of Combinational Majority and Minority Logic Networks",
International Mixed-Signals, Sensors and Systems Test Workshop 2008 (IMS3TW'08), pp. 1-6, 18/06/2008.
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"Reliability of wireless on-chip interconnects based on carbon nanotube antennas",
14th International Mixed-Signals, Sensors and Systems Test Workshop IMS3TW 2008, Vancouver BC, Canada, 06/2008.
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"Novel Interconnect Infrastructures for Massive Multicore Chips",
IEEE International Symposium on Circuits and Systems ISCAS 2008, Seattle WA, USA, 05/2008.
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2009
"Architecture for an External Input into a Molecular QCA Circuit",
Journal of Computational Electronics, vol. 8, issue 1: Springer, pp. 35-42, 03/2009.
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"Modeling and Evaluating Errors due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits",
Journal of Electronic Testing: Theory and Applications (JETTA), vol. 25, issue 1, pp. 55-66, 02/2009.
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2010
"Analysis of Field-Driven Clocking for Molecular Quantum-Dot Cellular Automata",
Journal of Computational Electronics, vol. 9, issue 1, pp. 16-30, 2010.
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"Investigation of the Various Impacts of Curvature on the Optical Absorption Properties of Carbon Nanotubes",
Pacific Center for Advanced Materials and Microstructures (PCAMM) 15th Annual Meeting, 12/2010.
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"Optical Transitions in Semiconducting Zigzag Carbon Nanotubes with Small Diameters: A First-Principles Broad-Range Study",
Physical Review B: Condensed Matter and Materials Physics, vol. 82, pp. 10 , 08/2010.
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"Curvature Effects on Optical Transitions in Semiconducting Carbon Nanotubes with Small Diameters",
11th International Conference on the Science and Application of Nanotubes (NT10), 06/2010.
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2011
"Tight-binding Model Including the Effect of Curvature for Calculating the Electronic and Optical Properties of Small-Diameter Semiconducting Carbon Nanotubes",
15th Canadian Semiconductor Science and Technology Conference, 08/2011.
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"Effect of Variations in Carbon-Carbon Bond Lengths on the Optical Absorption Properties of Different Carbon Nanotubes",
12th International Conference on the Science and Application of Nanotubes (NT11), 07/2011.
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2012
"Diameter Dependence of the Effect of Light Polarization on Interband Transitions in Zigzag Carbon Nanotubes",
56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN 2012), 05/2012.
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