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Filters: author is SalehA
"A scalable communication-centric SoC interconnect architecture",
Proceedings. 5th International Symposium on Quality Electronic Design, San Jose, CA, USA, IEEE Comput. Soc, pp. 343-8, 2004 .
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"Analog IP design flow for SoC applications",
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (Cat. No.03CH37430), vol. vol.4, Bangkok, Thailand, IEEE, pp. 676-9, 2003 .
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B
"BIST for network-on-chip interconnect infrastructures",
Proceedings. 24th IEEE VLSI Test Symposium, Berkeley, CA, USA, IEEE Computer Society, pp. 6 pp., 2006 .
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D
"Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip",
Integr. VLSI J. (Netherlands), vol. 40, pp. 149-60, feb.
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"Design of a switch for network on chip applications",
Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (Cat. No.03CH37430), vol. vol.5, Bangkok, Thailand, IEEE, pp. 217-20, 2003 .
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"Dedicated autonomous scan-based testing (DAST) for embedded cores",
Proceedings International Test Conference 2002 (Cat. No.02CH37382), Baltimore, MD, USA, IEEE, pp. 1176-83, 2002 .
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E
"Effect of traffic localization on energy dissipation in NoC-based interconnect",
IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat. No. 05CH37618), vol. Vol. 2, Kobe, Japan, IEEE, pp. 1774-7, 2005 .
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"Evaluation of MP-SoC interconnect architectures: a case study",
4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada, IEEE Comput. Soc, pp. 253-6, 2004 .
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F
"Field-emission-assisted approach to dry micro-electro-discharge machining of carbon-nanotube forests",
Journal of Applied Physics, vol. 110, issue 10, 10/2011.
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H
"High-precision dry micro-electro-discharge machining of carbon-nanotube forests with ultralow discharge energy",
IEEE 25th International Conference on Micro Electro Mechanical Systems (MEMS), 29/01/2012.
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"High-throughput switch-based interconnect for future SoCs",
Proceedings 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, Calgary, Alta., Canada, IEEE Comput. Soc, pp. 304-10, 2003 .
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M
"Methodologies and algorithms for testing switch-based NoC interconnects",
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, CA, USA, IEEE Comput. Soc, pp. 238-46, 2005 .
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N
"NoC interconnect yield improvement using crosspoint redundancy",
2006 21st IEEE International Symposium On Defect and Fault Tolerance in VLSI Systems, Arlington, VA, USA, IEEE Computer Society, pp. 9 pp., 2006 .
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O
"On-line fault detection and location for NoC interconnects",
12th IEEE International On-Line Testing Symposium, Lake Como, Italy, IEEE Comput. Soc, pp. 6 pp., 2006 .
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P
"Performance evaluation and design trade-offs for network-on-chip interconnect architectures",
IEEE Trans. Comput. (USA), vol. 54, pp. 1025-40, 2005 .
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S
"System-on-chip: reuse and integration",
Proc. IEEE (USA), vol. 94, pp. 1050-69, jun.
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"Switch-based interconnect architecture for future systems on chip",
Proc. SPIE - Int. Soc. Opt. Eng. (USA), vol. 5117, Maspalomas, Gran Canaria, Spain, SPIE-Int. Soc. Opt. Eng, pp. 228-37, 2003 .
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T
"Timing analysis of network on chip architectures for MP-SoC platforms",
Microelectron. J. (UK), vol. 36, pp. 833-45, sep.
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