Publications
Filters: keyword is timing2004
"A scalable communication-centric SoC interconnect architecture",
Proceedings. 5th International Symposium on Quality Electronic Design, San Jose, CA, USA, IEEE Comput. Soc, pp. 343-8, 2004 .
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2003
"Reducing test time of embedded SRAMs",
Records of the 2003 IEEE International Workshop on Memory Technology, Design and Testing, San Jose, CA, USA, IEEE, pp. 47-52, 2003 .
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"Yield, overall test environment timing accuracy, and defect level trade-offs for high-speed interconnect device testing",
Proceedings of the Twelfth Asian Symposium, ATS 2003, Xi'an, China, IEEE Comput. Soc, pp. 348-53, 2003 .
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