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Guangrui.Xia

Abstract

Near-surface Stresses in Silicon around Cu-filled and CNT-filled Through Silicon Vias

Project Description

The technology of through silicon via (TSV) is one of the most promising enablers for 3-D integration of circuits and systems. By providing direct die-to-die connections to form stacked structures in 3-D integration, better electrical performance and lower power consumption can be achieved [Knickerbocker, 2008] [Garrou, 2008]. Copper is widely used as the via-filling material because copper is compatible with the back-end of line (BEOL) processes along with appropriate electrical and mechanical properties. However, due to the relatively large mismatch of coefficients of thermal expansion (CTE) between silicon (2.3 ppm/⁰C) and copper (17 ppm/⁰C) [Jiang, 2013], embedded Cu TSVs in silicon ICs can induce substantial thermo-mechanical stresses during temperature ramps in fabrication. The TSV-induced stresses can cause undesirable mobility shifts in devices through the piezoresistivity effect [Thompson, 2006] [Karmarker, 2009] and reliability problems such as copper via pumping and interfacial delamination [Ranganathan, 2008] [Selvanayagam, 2009] [Lu, 2009] [Lu, 2010] [Ryu, 2011].

Recently, carbon nanotubes (CNTs) have emerged as an alternative TSV filling material due to its superior thermal conductivity (k) and low electrical resistivity (ρ) [Sinha, 2010]. It was reported that even air-filled CNT bundles had conductivities a few times higher than Cu [Abdul Kadir Kureshi, 2009]. Due to the negative axial CTE of CNTs [Sinha, 2010], it is expected that CNT should have different thermomechanical behaviors during the thermal processes compared with Cu, which may overcome the reliability problems such as via extrusion and interfacial delamination caused by Cu-filled TSVs. However, the stress field around CNT-filled TSVs has not been studied well.

Raman spectroscopy-based temperature dependent stress study was first used in our recent work [Zhu 2015]. Together with stress simulations, that work provided evidences that the near surface stresses are not only from the CTE-mismatch effect, but also from the pre-existing stress before Cu filling [Zhu 2015]. In this paper, this approach was further used to study the near surface stresses around Cu-filled TSVs, Cu-etched TSVs, CNT-filled TSVs and void vias without filling. The comparison between void vias and filled vias enabled us to prove our hypothesis on the “pre-existing” stress in Ref. [Zhu 2015]. Moreover, different stress components are compared for Cu-filled and CNT-filled TSVs.

Faculty Supervisor(s)

    Guangrui.Xia   

Researchers(s)

       

Research Area(s)

    Electronics